S5 vs Samsung Exynos 9110
S5
Samsung Exynos 9110
|
2 Cores
2 Threads
1.59GHz Clock
|
2 Cores
2 Threads
1.15GHz Clock
|
|
Socket
Unknown
|
Socket
Unknown
|
|
iGPU
S5
140 GFLOPS FP32
|
iGPU
Mali-T720 MP1 667MHz
10 GFLOPS FP32
|
|
|
S5 - 12.8GB/s
x1
Exynos 9110 - 25.6GB/s
x2
|
|
S5 - 2W
x1
Exynos 9110 - 3W
x1.5
|
|
S5 - 140 GFLOPS FP32
x14
Exynos 9110 - 10 GFLOPS FP32
x1
|
0%
|
0%
|
|
0%
|
0%
|
|
0%
|
0%
|
|
0%
|
0%
|
|
Manufacturer
Apple
|
Manufacturer
Samsung
|
|
Architecture
Apple Silicon 8
|
Architecture
ARMv8.0-A
|
|
Family
S Series
|
Family
-
|
|
Instruction Set (ISA)
AArch64
|
Instruction Set (ISA)
AArch64
|
|
Codename
Tempest
|
Codename
Cortex-A53
|
|
Market Segment
Watch
|
Market Segment
Watch
|
|
Release Date
9/25/2019
|
Release Date
8/1/2018
|
|
Foundry
TSMC
|
Foundry
Samsung
|
|
Node
N7
|
Node
10LPP
|
|
Die Size
Unknown
|
Die Size
Unknown
|
|
Transistor Count
Unknown
|
Transistor Count
Unknown
|
|
Unknown
|
Unknown
|
|
2 Cores
|
2 Cores
|
|
2 Threads
|
2 Threads
|
|
1.59GHz
|
1.15GHz
|
|
Overclocking
Locked
|
Overclocking
Locked
|
|
Integrated Chipset
|
Integrated Chipset
|
|
L0 Instruction
|
L0 Instruction
|
|
L0 Data
|
L0 Data
|
|
L1 Instruction
32KB/Core
4-way set associative
|
L1 Instruction
-
-
|
|
L1 Data
32KB/Core
4-way set associative
|
L1 Data
-
-
|
|
L2
2MB Shared
16-way set associative
|
L2
-
-
|
|
Channels
1
|
Channels
2
|
|
Max Memory
1GB
|
|
|
ECC
Not Supported
|
ECC
Not Supported
|
|
Bus Width/Channel
32Bit
Bus Width
32Bit
|
Bus Width/Channel
32Bit
Bus Width
64Bit
|
|
Clock
1600MHz
Transfer Rate
3200MT/s
|
Clock
1600MHz
Transfer Rate
3200MT/s
|
|
Bandwidth/Channel
12.8GB/s
Bandwidth
12.8GB/s
|
Bandwidth/Channel
12.8GB/s
Bandwidth
25.6GB/s
|
|
TDP
2W
|
TDP
3W
|
|
Included Cooler
|
Included Cooler
|
|
No PCIe
|
No PCIe
|
|
S5
128 Shaders
562MHz
140 GFLOPS FP32
|
Mali-T720 MP1 667MHz
10 Shaders
667MHz
10 GFLOPS FP32
|
|
No NPU
|
|
|
2 Cores
|
-
|
|
1.3 TOPS FP16
|
-
|
|
No Cellular
|
Modem
Samsung
Shannon 150/75
4G
|
|
Speed
Up to 150Mbps Download
Up to 75Mbps Upload
|
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